STATICEXTENDEDWAIT

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Interpret as STATICEXTENDEDWAIT

Time for long static memory read and write transfers.

EXTENDEDWAIT	Extended wait time out. 16 clock cycles (POR reset value). The delay is in CCLK cycles. 0x0 = 16 clock cycles. 0x1 - 0x3FF = (n+1) x16 clock cycles.
RESERVED	Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

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